MyLogic Station V5.1 is the schematic capture with logic-level simulator solution to provide easy to use and cost effective way of making prototypes. MyLogic Station V5.1 enables FPGA design by generating schematic netlist to structural VHDL or EDIF netlist. And it accepts VHDL codes or EDIF to generate the schematic data.
Schematic Capture/Logic Simulator, Schematic Generation from EDIF
Supports a various drawing modes
Schematic, Symbol, State Table, Truth Table, Logic Equation (Boolean Equation), ROM/RAM Table
Structural VHDL Netlist Generation
SchEd : Schematic Editor : State Diagram Editor
Supports on-line circuit check.
Structural VHDL generation.
Boolean Equation.
Schematic generation from EDIF netlist.
MState Diagram Editor.
EDIF netlist generation.
MySim : Logic Simulator
Logic level simulator.
Supports typing commands.
Waveform Analyzer.
Easy to draw waveform for stimulus.
Test bench generation for VHDL simulation.
Logic2EDIF : EDIF Netlist Generator
SchGen (EDIF2Logic) : Schematic Generator